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CoreU1LL UTOPIA Level 1 Link-Layer Interface
Product Summary
Intended Use
?
IDE and Industry Standard Synthesis and
Simulation Tools
RTL Version
– VHDL Source Code
?
Standard UTOPIA Level 1 Interface to any ATM
– Core Synthesis and Simulation Scripts
PHY-Layer Device
?
Actel-Developed Testbench (VHDL) Fully
Supported by Industry-Standard Simulation Tools
Key Features
?
Standard 8-Bit, 25 MHz UTOPIA Level 1 Link-Layer
Design Tools Support
?
(Master) Interface Complies with the ATM Forum
UTOPIA Specification, Level 1 Version 2.01 (af-phy-
0017.000)
Separate Tx and Rx Clocks and Interface Pins
?
?
Simulation: VITAL-Compliant VHDL and OVI-
Compliant Verilog Simulators
Synthesis: LeonardoSpectrum TM , Synplify ? , Design
Compiler ? , FPGA Compiler TM , and FPGA Express TM
?
Supports Cell-Level Handshake for 53- or 54-byte
ATM Cells with Automatic Add/Drop of the UDF2
Field in the ATM Header in 53-byte Mode
Contents
?
16-Bit (54-byte) User Interfaces can be Used
Directly or Bolt-Up to One of Actel's ATM Cell
Buffer Blocks: ATMBUFx
General Description ...................................................
Device Requirements .................................................
UTOPIA Interface .......................................................
1
2
2
Supported Families
User Interface .............................................................
3
?
?
?
?
Fusion
ProASIC3/E
ProASIC PLUS?
Axcelerator ?
Ordering Information ................................................
List of Changes ...........................................................
Datasheet Categories .................................................
6
7
7
Core Deliverables
General Description
?
Netlist Version
– Compiled RTL Simulation Model Fully
Supported in the Actel Libero ? Integrated
Design Environment (IDE)
– Structural VHDL and Verilog Netlists (with and
without I/O Pads) Compatible with Actel Libero
RX
Utopia
CoreU1LL is a UTOPIA Level 1 Link-Layer (Master)
interface core that connects directly to any ATM PHY-
Layer (Slave) device and user logic (or optional ATM cell
buffer blocks) to provide an interface between the PHY-
Layer device and a non-standard Link-Layer device or
user logic ( Figure 1 ).
CoreATMBUF3
Level 1
PHY-Layer
Device
TX
CoreU1LL
CoreATMBUF3
User
Logic
Other
Device
Figure 1 ? Block Diagram
December 2005
? 2005 Actel Corporation
v 4 .0
1
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相关代理商/技术参数
COREU1LL-EV 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-SN 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-SR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-UR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-XX 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1PHY-AN 制造商:Microsemi Corporation 功能描述:COREU1PHY-UTOPIA LEVEL 1 PHY INTERFACE - Virtual or Non-Physical Inventory (Software & Literature)
COREU1PHY-AR 功能描述:IP MODULE COREU1PHY RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384
COREU1PHY-EV 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1PHY - UTOPIA Level 1 PHY Interface